This invention relates to a digital-to-analog (D/A) converter circuit for applications which have the combined objectives of: (A) accuracies of the order of 1 part in 1000 parts, (B) circuit settling times of the order of 50 nanoseconds or less, and (C) power consumption of the order of five milliwatts per bit or less.
There is much need for an analog-to-digital converter having the foregoing combination of performance objectives in such areas of technology as control systems for satelite vehicles or airborne fire control systems. Further, if such a circuit could be constructed at a cost comparable to that of existing general purpose converters, it would offer the advantage of low-power consumption for any application.
It is a well recognized design principle that the tolerances of accuracy of the voltage output from the driver stages at the front end of a converter circuit are a primary consideration in achieving D/A converter accuracy. Prior to the advent of field effect transistor (F.E.T.) technology, there existed a dichotomy in trying to achieve both the accuracy and low power. The active circuit devices which existed prior to F.E.T. technology posed problems of "voltage offset"in circuit constructions. Voltage offset is the unpredictable variations in the output voltage of an active device. This was particularly a problem where a stage had to drive lower impedance loads. On the other hand, the primary design approach for improving the accuracy of resistive scaling networks involves decreasing the impedance load. One attempt to overcome this dichotomy was to employ a saturation drive complementary grounded-emitter bipolar transistor switch as the drive stage. However, the high base current drive required for low offset resulted in the disadvantage of a large stored charge in the base regions of the device. This, in turn, placed an unacceptable constraint upon settling times, as well as undesired power dissipation. For a discussion of the difficulties of this approach, see "Digital-To-Analog Converter Handbook" published in 1970 by Hybrid Systems Corporation of Burlington, Massachusetts. U.S. Pat. No. 3,014,211 to H. C. Bussey is an example of another approach to overcoming this dichotomy. There, the patentee overcomes the voltage offset problem by means of a network of resistors and back-to-back Zener diodes, to provide two level clamping in a circuit path employing a conduction control device as the switch device. The implementation disclosed in that patent is inherently contrary to a low power consumption objective, because of the high current flows involved. It is also contrary to the objective of high circuit settling speeds because of the high RC time constants connected with the resistive circuits, and the capacitance exhibited by the Zener diodes. Further, it would be difficult to achieve a high degree of accuracy due to the inherent mismatch in Zener voltages initially and with temperature variation.
The advent of junction-type Field Effect Transistor (FET) devices appeared to offer a solution to the problem of meeting the three combined objectives. These devices are known to work well in complementary switch configurations for purposes of providing accurate and high-speed driver stages. However, it can be shown that the objective of accuracy is primarily dependent upon very percise matching of individual devices, which can only be achieved by the fabrication of a multiplicity of these devices as a complete integrated circuit system on a single substrate. Whatever the reason, junction FET's are not available, or at least not commercially available, in this mode of fabrication.
General (in contrast to complementary) Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) devices are commercially available in modes of fabrication providing units having high packaging density on a single substrate, but not available with the high degree of match needed for high order D/A accuracies. Employing these devices for Tee configuration driver stages of high accuracy analog-to-digital converters is known. However, this configuration of driver necessitates the employment of high impedance ladder-type binary scaling networks which redue the speed of the D/A. Examples of these are the U.S. Pat. No. 3,755,807 to J. L. Brown and U.S. Pat. No. 3,646,587 to E. L. Shaffstall, et al. Also, the Tee configuration involves power consumption levels which substantially exceed five milliwatts per bit.
The advent of Complementary Metal-Oxide-Semiconductor-Field-Effect-Transistors (CMOSFET) devices also had obstacles to their use in D/A converters. Prior to the present invention, the well-known nonsymmetrical operating characteristics of their constituent P-channel and N-channel elements was considered a serious obstacle to accuracy. This nonsymmetrical behavior is described in detail in the following publications: RCA Solid State Data Book Series SSD-203A, 1973 Edition, published by RCA Corporation, Somerville, NJ, pps. 395-397, and McMos Integrated Circuits Data Book published by Motorola, Inc, 1973 pps. 1-3 and 1-4, and 2-9 and 2-13 and 2-14. The foregoing text materials also describe the substantial variation with temperature of the operating characteristics of CMOSFET devices, which prior to the present invention was considered a serious obstacle to any application under varying temperature conditions.